World class innovation in design constraint development and verification solutions
Ausdia Inc. is an experienced, trusted technology company solving design's toughest problems and transforming SoC design. The company is focused on delivering proven design constraint development and verification solutions that complement all implementation and timing signoff flows.
Ausdia's groundbreaking approach represents a new way for STA developers and users to enable massive productivity gains across the design flow resulting in shrinking design time which ultimately leads to a significant saving in design costs. Founded in 2006, Ausdia has a combined experience of over 60 years in EDA development, chip engineering and methodology.
Ausdia's flagship platform – TimevisionTM – allows STA engineers to dramatically increase their productivity by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data.
Timevision brings this same capability to RTL designers, who are often under extreme pressure to be involved with timing closure (but lack the time available to dive into gate-level issues). The platform also assists implementation engineers in trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).
TimevisionTM: Design Constraint Technology
Market situation & the need for design constraint technology:
Silicon design is becoming vastly more complicated and costly, and harder to design and verify. Today’s SoCs drive this exploding complexity – thanks to raw design size, increasing use of IP blocks, advanced technology node, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. There is a demand for a comprehensive product to generate and validate design constraints that correlate with static timing analysis engines to ensure design correctness.
The huge cost of an error in constraints, clocking or timing often forces design teams to adopt a minimization strategy – designing a completely minimal, safe set of timing constraints that are the least prone to error. Experienced leaders in the silicon design field recognize this as a complex, multi-faceted problem that requires a variety of capabilities and techniques to attack. Simple structural or semantic tools and approaches will only catch simple problems while emitting copious numbers of false-positive errors requiring designer review. The solution should aid in the goal of helping the design team create design constraints that cover the requirements of the design, allowing it to meet its power, performance and area goals while minimizing the risk of a respin due to a clocking or timing issue.
TimevisionTM is a comprehensive platform solution to generate and validate timing constraints that correlate with static timing analysis engines to ensure design correctness. Using multi-core software architecture, patented analysis algorithms, and innovative formal verification technology, the founders of Ausdia created Timevision to handle large, complex SoC designs–especially above 100+ million instances.