Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors. This includes streamlining UVM-based testbenches for IP verification, synchronizing software and hardware tests for large system-on-chips (SoCs), and simplifying test sets for hardware emulation and post-fabricated silicon. The Breker solutions are designed to layer into existing environments.
Our Trek family of products is proven in production at many leading semiconductor companies worldwide. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), Breker has earned a reputation for dramatically reducing verification schedules in advanced development environments. The company’s solutions enable design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easily reuse verification knowledge.
TrekSoC and TrekSoC-Si help customers develop intuitive models, based on the PSS, to describe the verification space, and then use these models to automatically generate SoC test cases including stimulus, expected results and coverage detail. TrekUVM uses the same scenario model format to generate Universal Verification Methodology (UVM) test cases for transactional testbenches, all but eliminating the notorious complexity of UVM sequence authoring. These solutions enable test reuse across simulation, emulation, prototyping and actual silicon, eliminating redundant effort across the development flow.
Breker also produces a range of “apps” to provide push button solutions for common system verification problems. The Cache Coherency TrekApp verifies system-level coherency in a multiprocessor SoC. The Power Analysis TrekApp automates the verification of power domain reset states in a multi power domain device. The ARMv8 TrekApp handles typical processor test issues and is focused primarily on the ARM device range. Customers can begin testing earlier in the process, even before RTL coding is complete, and expand incrementally to realize greater coverage.
Breker has grown steadily, partnering with diverse design groups at leading-edge semiconductor companies. Our dynamic team shares one vision, to drive the evolution of verification technology with a single-minded focus on our customers’ success. Breker is a venture-backed company headquartered in Silicon Valley with a support network operating worldwide.
Breker Products and Apps
The Breker tool suite and TrekApps have been proven in production at many leading semiconductor companies worldwide, earning a reputation for dramatic verification schedule reduction in advanced development environments. Breker’s solutions enable design managers and verification engineers to realize measurable productivity gains through GRAPH-based scenario description, speed coverage closure by PORTING the same tests across verification platforms, and easily SHARE verification knowledge.
TrekUVM
TrekUVM uses the same scenario model format to generate Universal Verification Methodology (UVM) test cases for transactional testbenches, all but eliminating the notorious complexity of UVM sequence authoring.
TrekSoc
TrekSoC helps customers develop intuitive models based on the PSS to describe the verification space, and then use these models to automatically generate SoC test cases including stimulus, expected results and coverage detail.
TrekSoc-Si
TrekSoC-Si enables all of the testbench capability contained in TrekUVM and TrekSoC to be applied to hardware verification solutions including Emulation, Prototyping Systems and to the final device, post-fabrication.
TrekApps
The ARMv8 TrekApp provides a broad range of ARMv8 integration verification functions.
The Cache Coherency TrekApp verifies system-level coherency in a multiprocessor SoC.
The Power Management TrekApp automates the verification of power domain shutdown and bring up.
The RISC-V TrekApp generates system integration tests for Open Architecture RISC-V processors.
The Security TrekApp synthesizes test content to verify IC protected regions.
TrekDAE
The Design Analysis Environment user interface provides unique visual graph construction, graph visualization, and multi-threaded runtime test inspection capabilities. It operates across all of the Breker tool suite and TrekApps, enabling a consistent use and feel for the tools. The new visual graph editor allows for fast scenario construction and comprehension.
Scenario Modeling
The entire tool suite makes use of graph-based scenario models created using either the new Accellera Portable Stimulus Standard DSL or C++ formats, or coded in native C++. The models may also be entered using the Breker visual editor, or generated from one of the TrekApps. These modeling options provide easy methods to build powerful and complete models of verification intent.
