Verific Design Automation builds SystemVerilog, VHDL, and UPF Parser Platforms which enable its customers to develop advanced EDA products quickly and at low cost.
Verific's Parser Platforms are distributed as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac, and Windows operating systems.
Verific's Parser Platforms are in production and development use today at numerous companies worldwide, from EDA start-ups to established Fortune 500 semiconductor vendors.
To view some of the EDA products you can find us in, click here.
Verific’s SystemVerilog parser supports the entire IEEE-1800 standard and is compatible with leading industry simulators Incisive, QuestaSim and VCS.
Verific’s UPF parser supports the entire IEEE-1801 standard and is integrated with its SystemVerilog and VHDL parsers.
Verific’s VHDL parser supports the entire IEEE-1076 standard and is compatible with leading industry simulators Incisive, QuestaSim and VCS.