Zvi Or-Bach, the CEO of MonolithIC 3D, a company specializing in 3D semiconductor integration, presented an analysis in 2014 revealing that the per-transistor cost had ceased to decrease at 28nm. This finding was recently supported by Milind Shah from Google, demonstrating that the per-transistor cost for 100 million gates had actually increased since 2012 when a 28nm planar process technology was put into mass production by TSMC, as reported by Semiconductor Digest.
The industry has been worried about diminishing returns for per-transistor costs with new nodes for quite some time. The latest chipmaking process technologies, such as 7nm, 5nm, and 3nm, require more sophisticated fab tools that cost hundreds of millions of dollars, bringing the cost of leading-edge fabs to levels from $20 billion to $30 billion. This increased complexity and expense make production at leading-edge nodes very costly. However, considering the broader view, while chipmaking has become more complex and expensive over the years, it remains logical to evaluate the larger implications.
Based on the graph presented by Milind Shah from Google at the industry tradeshow IEDM, the cost of 100 million transistors normalized to 28nm is either flat or even increasing. This lack of cost scaling makes it less appealing for some chip designs to adopt the latest nodes and more appealing to disaggregate designs into chiplets instead of producing monolithic designs crafted of a single piece of silicon using a leading-edge node to optimize costs and performance.
Examples of disaggregated designs in the client computing space include AMD's Ryzen desktop CPUs and Intel's Meteor Lake laptop CPUs, which consist of three or four chiplets made on different process technologies at different factories. In the data center realm, AMD's EPYC data center CPUs serve as another example. Larger companies like AMD and Intel can carefully assess their design options and build products using the best technologies available to them. However, for smaller manufacturers, it may not be as straightforward.
Firstly, multi-chiplet designs tend to be more power-hungry than monolithic designs, making them less suitable for mobile devices. Secondly, multi-chiplet integration poses significant engineering challenges, and while companies like MonolithIC 3D offer multi-chiplet integration services using advanced packaging technologies, such as Intel's Foveros or TSMC's CoWoS, these services come with associated costs. Additionally, advanced packaging technologies are expensive, and obtaining CoWoS allocation is as challenging as securing a leading-edge node allocation.
Therefore, while new nodes may no longer make transistors cheaper, they still make sense for many designs that either cannot be efficiently disaggregated or are challenging to disaggregate due to manufacturing complexities.
