21.12.2024

MIT engineers have developed an innovative method for stacking electronic layers to produce high-performance 3D chips, dramatically increasing transistor density and enhancing AI hardware capabilities. As traditional semiconductor manufacturing approaches a limit on surface area transistor packing, the new technique focuses on building multiple transistor layers, akin to transforming a single-story building into a high-rise. This multilayered design could enable chips to handle considerably more complex data and functions than current technology allows.

A significant challenge in this realm has been the use of bulky silicon wafers, which can impede communication between stacked layers due to their thickness. The MIT team has overcome this obstacle by creating chips that do not rely on silicon wafer substrates, allowing layers to be built directly on top of each other without the need for thick silicon flooring. Their groundbreaking research, published in Nature, demonstrates the feasibility of fabricating multilayered chips with high-quality semiconducting materials grown directly on each other.

The researchers' method enables the construction of advanced transistors, memory, and logic elements on various crystalline surfaces. This capability is crucial for developing fast and powerful AI hardware, capable of competing with today’s supercomputers and supporting significant data storage, potentially matching that of entire data centers. Jeehwan Kim, an associate professor at MIT, states that this breakthrough creates immense opportunities within the semiconductor field by allowing stacking without conventional limitations.

The team previously established a method for growing high-quality semiconductor materials on amorphous surfaces and found a way to maintain structural integrity at lower temperatures critical for preserving existing circuitry. They drew inspiration from metallurgical practices, where nucleation of solid crystals occurs more readily at edges, enabling crystallization at lower temperatures. This adjustment allows them to grow single-crystalline transition-metal dichalcogenides (TMDs) directly on silicon wafers already containing circuitry, significantly lowering processing temperatures to around 380 degrees Celsius.

The researchers successfully fabricated a multilayered chip using alternating layers of two distinct TMDs: molybdenum disulfide and tungsten diselenide, which are capable of functioning as n-type and p-type transistors, respectively. This technique allows the configuration of a chip that can more than double the density of semiconducting components, particularly benefiting CMOS technology, a fundamental element of modern logic circuitry.

The approach not only results in a 3D logic chip but also permits the integration of 3D memory, facilitating improved communication between layers. The conventional methods of creating 3D chips often involve physical drilling through silicon, limiting the number of layers and overall efficiency. The new growth-based method addresses these issues holistically.

To further advance the commercialization of their technology, Kim has launched a startup called FS2 (Future Semiconductor 2D Materials) focused on scaling the chip designs for professional AI applications. This research enhances the potential for creating more complex, efficient, and powerful electronic devices, marking a significant leap forward for the semiconductor industry and AI hardware. The team aims to scale their small-scale device arrays to demonstrate full AI chip functionalities in the future.