SK Hynix Inc. plans to adopt the cutting-edge 3-nanometer process technology for the production of its customized HBM4 chips, set to be manufactured in the second half of 2025. The South Korean semiconductor firm initially intended to create the sixth-generation high-bandwidth memory (HBM4) on a 5 nm node but has since switched to the more advanced 3 nm process in collaboration with TSMC, the leading foundry. This shift was driven by requests from major clients like Nvidia Corp., who seek more advanced memory options.
Sources suggest that SK Hynix will unveil a prototype of the HBM4 design that utilizes a vertically stacked architecture on a 3 nm base die as early as March. This new design is projected to enhance performance by 20-30% compared to HBM4 chips with a 5 nm base die. Currently, Nvidia's graphic processing units (GPUs) utilize 4 nm HBM chips.
The decision to implement the 3 nm process aligns with SK Hynix's strategy to strengthen its ties with major U.S. tech companies, such as Nvidia, Google, and Microsoft, thereby reducing reliance on Chinese markets amid increasing U.S. export controls. This comes on the heels of Washington's announcement of new semiconductor export restrictions targeting China, which includes HBM technology.
SK Hynix dominates the global HBM market, holding approximately 50% of the share and supplying a considerable portion of its products to Nvidia, the largest buyer of AI chips worldwide. The production of HBM4 using a 3 nm base die will further distinguish SK Hynix from competitors like Samsung Electronics, which intends to pursue a 4 nm foundry process for its HBM4 offerings.
For general-purpose HBM4, SK Hynix will also utilize a 12 nm process in partnership with TSMC. Historically, the company manufactured its fifth-generation HBM3E using its technology base dies, but for HBM4, it has opted for TSMC's advanced process.
TSMC, known for mass-producing 3 nm memory chips for devices like Apple iPhones and MacBooks, enhances SK Hynix’s capacity. There is a direct correlation between the reduction in chip linewidth and the number of chips that can be placed on a substrate or wafer, emphasizing the benefits of smaller nanometer processes.
The urgency in developing HBM4 chips is underscored by a recent request from Nvidia CEO Jensen Huang, who urged SK Group Chairman Chey Tae-won to accelerate the timeline for 12-layer HBM4 chips by six months, bringing it up from early 2026 to late 2025. Additionally, Tesla has reached out to both SK Hynix and Samsung for samples of HBM4 prototypes intended for general use, with plans to select a supplier after testing.
This strategic focus on innovation and advanced production processes positions SK Hynix well in the competitive semiconductor landscape, responding to the evolving demands of industry leaders.
