TSMC has announced that it is set to begin mass production of chips using its A16 process technology, a 1.6nm-class node, by late 2016, as revealed during its European Open Innovation Platform Ecosystem Forum in Amsterdam. This new technology features the Super Power Rail (SPR) backside power delivery network (BSPDN), which facilitates improved power delivery by routing power through the chip's back side, enabling higher transistor density. While this innovation resolves certain challenges in power management, it introduces new complexities that require additional design efforts.
The A16 process will incorporate gate-all-around (GAAFET) nanosheet transistors, similar in architecture to TSMC's N2-series (2nm-class) technology. Compared to the existing N2P fabrication process, A16 is expected to offer an 8%-10% performance improvement at equivalent voltage levels, or achieve a 15%-20% reduction in power consumption at the same frequency and transistor count. Moreover, TSMC anticipates a 1.07x to 1.10x increase in chip density for high-performance AI processors, depending on the types of transistors and associated libraries utilized.
According to Ken Wang, TSMC’s director of design solution exploration, the architectural similarities between the A16 and N2 transistors simplify the migration process for design layouts. He noted that logic layout changes from N2P to A16 would be relatively straightforward due to the similarity in cell structures and design patterns. An important aspect of the A16 is its incorporation of the NanoFlex feature from its predecessor, N2, enhancing driving strength.
The Super Power Rail connects power delivery directly to each transistor's source and drain through specialized contacts, minimizing wire length and resistance, which leads to improved performance and energy efficiency. This implementation is among the most complex BSPDN designs, surpassing Intel's Power Via in intricacy.
Nevertheless, the advanced BSPDN requires a comprehensive redesign of the power delivery network, compelling chip designers to adopt new strategies for placement and routing. Additionally, designers must address thermal management issues, as heat distribution will be more challenging due to wire placements. The transition to chips utilizing a backside power delivery network necessitates updated methods across various design processes, including thermal-aware placement, clock tree construction, and different analyses for IR drop and thermal impacts.
