According to industry sources, TSMC is exploring an innovative chip packaging method using rectangular panel substrates instead of round wafers, potentially boosting chip set production. This new method represents a significant technological shift for TSMC but is still in early research stages, requiring time for commercialization.
The rectangular substrates being tested are sized at 510mm x 515mm, offering three times more usable area than standard 12-inch circular wafers and optimizing space utilization. TSMC, known for its advanced chip technologies, currently uses 12-inch wafers and is enhancing capacity to meet growing demand. The Taichung facility expansion in Taiwan caters to Nvidia, while the Tainan facility supports Amazon and Alchip .
TSMC mentioned it is closely following advancements in advanced packaging technologies, including panel-level packaging. Previously considered less advanced, chip packaging has now become crucial in driving semiconductor innovation. For example, Nvidia's AI computing chips like the H200 and B200 rely on TSMC's CoWoS technology for faster data processing. Analysts suggest TSMC may need to adopt rectangular substrates soon to meet the increasing demand for AI chipsets requiring more chips per package. Mark Li from Bernstein Research highlighted this potential shift in substrate adoption by TSMC due to the rising demands of AI chipsets.
