Intel and Research Fab Microelectronics German (FMD) have collaborated on a "2030+ research roadmap for 3D heterogeneous integration." The objective of this initiative is to develop technology that is future proof well beyond 2030. The workshops involved not only Intel and FMD but also various German and European industrial players, including materials and process equipment providers, chip designers, assemblers, board manufacturers, and integrators. Additionally, German and European organizations working on application domains that are likely to utilize the resulting technology were invited.
The research roadmap encompasses several essential aspects, such as material combinations, design strategies, manufacturing processes, and the concept of system and technology co-optimization (STCO). Additionally, the roadmap addresses testing and metrology, automation and data analysis, and modeling and simulation. The goal is to develop digital twins for these complex structures as early as possible.
One of the key focuses of this collaboration is the packaging of chiplets for specific applications. Chiplets are specialized components that work together to meet the specific requirements of an application. Customized packaging of these chiplets is crucial to achieve near-monolithic performance, high reliability, and cost-effectiveness. The packaging techniques involve either laying the chiplets side by side on a substrate (2.5D integration) or vertically stacking them on top of one another (3D integration).
The semiconductor industry has been moving towards 2.5D and 3D packaging to fit more compute, memory, and other functions into limited space. Intel and FMD recognized an opportunity to advance the state of the art in packaging when Robert Chau, director of Intel Europe Research and Intel senior fellow in Technology Development, relocated to Europe. The collaboration aims to target key application areas through joint research projects, with a particular focus on industries such as automotive and data centers.
The automotive sector poses unique challenges as all components must function reliably for 20 to 25 years. Safety compliance and the ability to withstand varying temperature conditions are additional considerations. In the data center industry, 3D packaging is critical for high-performance computing, enabling enhanced power efficiency and extending the capabilities of microelectronics.
To address the challenges and opportunities identified, joint research teams are being established at FMD with collaboration from Intel and other industry players. Hybrid bonding is one key area of focus for 3D integration, as it enables dense interconnection and stacking of chips vertically with direct copper-to-copper bonding. Architectural models for stacking and interconnecting silicon modules on organic boards are also being explored to provide high-reliability packaging for different industrial partners' applications.
The collaboration between Intel and FMD on the 2030+ research roadmap aligns with Intel Europe Research's commitment to partnering with other research institutions in Europe. The roadmap builds upon the industry's history of developing and executing successful roadmaps, which have contributed to the advancement of Moore's Law.
