Leaders in the semiconductor industry are shifting away from consolidating all transistors onto a single chip. Instead, they are breaking down their largest, most advanced chips into smaller silicon pieces known as chiplets. These chiplets can be manufactured with the most suitable process technology and then combined to replicate a unified system-on-chip (SoC). By incorporating diverse chiplets within a single package, these "multi-die" systems deliver enhanced performance across various applications from AI to RF.
Currently, companies have the flexibility to mix and match chiplets produced by different foundries utilizing varying process nodes, consolidating them into a system-in-package (SiP) with various advanced packaging techniques. However, integrating third-party chiplets into the package presents a challenge due to the absence of a standard die-to-die connection. In response, major players in the chip industry are aiming to introduce a new standard to bridge this gap, ushering in a new era of domain-specific accelerators in the process.
Intel and Synopsys are showcasing the potential by collaborating on the world's first multi-die system featuring chiplets linked by the Universal Chiplet Interconnect Express (UCIe). UCIe serves as a proposed die-to-die interface standard designed to streamline the integration of third-party chiplets. While initially a test chip, Synopsys affirms it underscores the companies' dedication to supporting an open ecosystem.
Although Intel initially presented the test chip at their "Innovation" event last year, Synopsys CEO Sassine Ghazi brought it to the forefront again during the company's recent annual conference.
The test chip, named Pike Creek, comprises an Intel UCIe IP chiplet based on Intel 3 process technology paired with a Synopsys UCIe IP chiplet produced on TSMC's 3-nm node. Employing UCIe for their interaction, the chiplets are physically linked through Intel's 2.5D advanced packaging technology—Embedded Multi-Die Interconnect Bridge (EMIB). Ghazi envisions this as the future of the semiconductor industry, combining multiple fabs, industry-standard UCIe IP sets, and modern EDA packaging solutions.
