TSMC is developing an enhanced version of its chip-on-wafer-on-substrate (CoWoS) packaging technology that will support system-in-packages (SiPs) over two times larger, the company disclosed at its North American Technology Symposium. These new packages will be massive, measuring 120x120mm, and will consume kilowatts of power, according to TSMC's projections.
The latest iteration of CoWoS technology allows TSMC to fabricate silicon interposers that are approximately 3.3 times larger than a photomask (858mm2). This enables logic, eight HBM3/HBM3E memory stacks, I/O, and other chiplets to occupy up to 2831 mm2 of space. The maximum substrate size is set at 80×80 mm. Notably, both AMD's Instinct MI300X and Nvidia's B200 utilize this technology, with Nvidia's B200 processor being larger than AMD's MI300X.
The upcoming CoWoS_L technology, expected to be operational by 2026, will support interposers around 5.5 times the size of a photomask, providing 4719 mm2 for logic, up to 12 HBM memory stacks, and other chiplets. These SiPs will necessitate larger substrates, likely 100x100 mm based on TSMC's plans, thus ruling out the use of OAM modules.
Continuing its innovation, in 2027, TSMC aims to introduce an iteration of CoWoS technology capable of accommodating interposers eight times or more the size of a photomask, offering chiplets a spacious 6,864 square mm. One proposed design involves four stacked systems-on-integrated chips (SoICs) paired with 12 HBM4 memory stacks and extra I/O dies. Such large-scale processors are anticipated to demand significant power consumption, likely in the range of thousands of watts, necessitating advanced cooling solutions. TSMC anticipates utilizing a 120x120mm substrate for these solutions.
Earlier this year, Broadcom showcased a custom-built AI processor featuring two logic dies and 12 HBM memory stacks. While specific details are scarce, this processor appears larger than AMD's Instinct MI300X and Nvidia's B200, although not as substantial as TSMC's ambitious plans for 2027.
