Ningbo ChipEx Semiconductor Co., Ltd was established in January 2013 with a total investment of 280 millions, and located in Hangzhou-Bay New Zoon, Ningbo (Exit of Hangzhou-Bay Bridge). ChipEx focused on Wafer Level CSP、FC-Bumping and other related business, also provide wafer testing, packaging design, packaging and testing for customers from local and overseas. Products are widely used in smart phones, tablet PCs, wearable electronic devices and other electronic products, expand to energy saving and environmental protection, intelligent home, bio-medical, networking automotive electronics and so on.

     ChipEx strengthen the sense of quality, with excellent quality and perfect service to meet customers’ needs, and passed ISO9001, ISO14000 and QC080000 certification.

     ChipEx’s purpose is to make the customers’ satisfaction with the quality, delivery, cost and service for the advanced IC packaging, and continuously improve the quality and technological innovation to meet customers’ needs, making the company developing rapidly.

Wafer Level Chip Scale Packaging is different from the traditional chip package (Sawing before packaging and testing, and the volume will be increased at least 20% than the original chip). This latest technology is firstly film deposited on the wafer, then litho, electrochemical deposition, packaging and testing will be go on, at last been sawed into the same size die as the chip scale, without going through the wire and filling process, the chip size is almost the same as bare chip after packaging. Packaging efficiency close to 100%, in line with consumer electronics products’ market trend of light, small, short and thin, and has a large density, low induction, low cost, good heat dissipation and so on. The advantages of packaging are more obvious while wafer size increases and die size decreases.

Copper pillar process is making copper-tin bumps on the surface of the chip for "point-of-connection" between the chips or the chips and the substrates by utilizing gluing, litho, electroplating and etching process and other production technology through the surface of the chip in the production of copper and tin bumps after wafer processing of the substrate circuit. The array of bumps on the die surface allows pin density to be higher due to the elimination of the traditional "wire bonding" to the surrounding metal, reducing the area of the chip to meet the performance requirements of the chip, low resistance, low parasitic capacitance, low inductance, low power consumption, low signal-to-noise ratio, low cost, and so on.

Redistribution Line changed the original design of the IC line contact I/O pads by through the wafer-level metal routing process and the bump process, so that IC can be applied to different packages. Wafer-level metal routing process is firstly the IC coated with an insulating layer of protection, and then exposed development to define new ways of the pattern, and then use the plating technology to create new metal lines to connect the original aluminum pad with the new convex block or gold pad, making a redistribution line. The metal lines of redistribution always are copper plating materials, also can be nickel-plated copper wire or nickel-palladium gold if needed. Thick copper structure will be the best choice for high-current and high-power devices due to its low resistance, high heat dissipation and low cost advantages.

      The advantages of redistribution line are as follows: change the circuit I/O original design, increase the added value of the original design; increase the I/O spacing, providing a larger area of the bump, reducing the stress between the substrate and components to increase the reliability of components; replace part of the IC circuit design, accelerate IC development time.

Electroplating solder Technology is making tin bumps on the chip pads by series processes such as coating, litho, electroplating and etching, and then using high temperature melting the bumps and been packaged, the IC size can significantly be reduced by this technology, and has a high density, low induction, low cost, good heat dissipation and so on. Wafer-level chip scale packaging is generally applicable to large-size solder balls placed on large pads and the solder technology applied in the manufacture of fine pitch and ultra-thin package of the small tin ball way. This technology successfully applied to flip and reflected its superiority.

Making TVS devices by using Wafer-Level Packaging technology can obviously reduce device size and significantly improve electrical performance and reliability, shorten the package time and lower cost, which was widely used in mobile phones, MP3 players, PDAs and digital cameras and other portable electronic products to provide protection and improve its reliability.



Products in categories