The recent news of Intel’s partnership with Arm to simplify mobile system-on-chip (SoC) designs for the 18A process at IFS has garnered significant media attention. However, what has gone relatively unnoticed is IFS's steady efforts in developing an extensive and varied ecosystem by assembling analog building blocks.
Through the IFS Accelerator IP Alliance Program, the company intends to assist its foundry customers in bringing their silicon products from concept to realization. To achieve this, IFS is incorporating pre-validated and reusable IP blocks to strengthen the path towards successful chip design.
Agile Analog, a UK-based supplier of analog IPs for power management and data conversion, has joined the IFS Accelerator IP Alliance Program, making its analog IP portfolio available to IFS's ecosystem. Meanwhile, Silicon Creations, a supplier of analog and mixed-signal IPs, has joined the program and will make its fractional-N synthesizer available for Intel 16 process technology IP ecosystem. Sofics, a provider of IP solutions for ESD, EOS, and EMC, has also joined the program and will bring its TakeCharge ESD technology to optimize on-chip ESD protection for FinFET designs. These partnerships will provide chip designers with access to high-quality analog IPs and support for their analog and mixed-signal design requirements.
Besides IP building blocks, IFS has a similar program for EDA tools and simulation solutions. Analog design solution providers are also joining the IFS Accelerator EDA Alliance Program. That underlines the critical significance of analog building blocks in IFS’s bid to develop a viable ecosystem around its open-system foundry model.
