Intel's CEO, Pat Gelsinger, has expressed the importance of larger mask sizes in the realm of high-NA EUV lithography, and potentially low-NA EUV, to facilitate the exposure of more wafer area in a single step. This advancement has the potential to eliminate design constraints and possibly enhance throughput.
The connection between mask size and field size, or the area of the wafer exposed in a single exposure step, is critical. The current industry standard for EUV field and mask sizes are 26 by 33 millimeters and 6 by 6 inches, respectively. To adapt to high-NA requirements, ASML and Zeiss doubled the magnification in one direction, resulting in a reduced field size of 26 by 16.5 millimeters. While ASML has bolstered the wafer stages to compensate for the diminished throughput, printing larger die sizes with the diminished fields presents challenges, as images must be 'stitched' together to form full-sized chips. Returning to the industry standard mask size may also lead to increased throughput.
Restoring the field size to its full capacity can be achieved by doubling the mask size to 6 by 12 inches. Initially rejected due to concerns regarding cost effectiveness in comparison to retaining the existing EUV mask infrastructure, Intel, the most fervent advocate of high-NA EUV, aims to reopen this discussion.
While the prospect of increasing mask size presents substantial challenges, such as the production of larger defect-free mask blanks and pellicles, as well as the need for equipment capable of manufacturing, inspecting, and handling masks of the new size, there is a consensus that this pivotal shift will require significant investment and commitment from the entire leading-edge chipmaker community. Thus far, leading chipmakers, such as Samsung and TSMC, have remained noncommittal on the matter. ASML, on the other hand, maintains an agnostic stance. A spokesperson for the equipment manufacturer has indicated a willingness to support the development of larger masks if prompted by the industry.
Gelsinger has articulated that, even without changes to the mask size, high-NA will prove to be cost-effective for Intel. This assertion stems from careful analysis, comparing the economics of double patterning with low-NA versus single patterning with high-NA. Gelsinger is relying on high-NA not only to deliver faster and lower-power transistors but also to achieve cost efficiencies, aligning with the overarching objective of restoring the economics of Moore's Law.
