SK Hynix is accelerating the development of a next-generation standard for 4D NAND flashes by mass-producing 238-layer products, the world's highest layers.
Author: Kim Eun-jin
The company introduced its 4D 2.0 technology at Flash Memory Summit 2022 (FMS 2022), which was held at the Santa Clara Convention Center in California early last month.
The event is the largest annual conference of the global NAND flash industry. In the event's keynote session, SK Hynix made a presentation jointly with Solidigm, its NAND solution subsidiary.
The core part of 4D 2.0 is "peri under cell," a technology that puts peripheral circuits, normally placed by the side, under cell circuits in order to reduce the chip size. By changing the architecture of the chip, SK Hynix could maximize space efficiency.
SK Hynix says that 4D 2.0 technology increases cell density horizontally. It uses a multi-site cell (MSC) method that divides a cell into two small-size cells through a microfabrication process to increase cell density. This makes it possible to secure a capacity that is difficult to attain through a single cell. Thus, chipmakers can cut the number of stacks while increasing cell density. Jung Woo-pyo, a researcher in charge of NAND flash design at SK hynix, said, “This technology stands a chance of becoming a next-generation standard.”
Meanwhile, SK Hynix recently provided samples of a 238-layer 512Gb TLC 4D NAND flash to customers. The product has the highest number of layers and the smallest size in the world. Its productivity is 34 percent higher than a 176-layer product. Its data transfer rate hits 2.4Gb per second, 50 percent faster than the previous generation product. Energy consumption is reduced by 21 percent, which helps chipmakers attain their ESG management goals.
“The latest achievement follows the development of the 176-layer NAND product in December 2020,” an SK Hynix official said. “We plan to start mass production of the new chip in the first half of 2023.”