TSMC recently discussed the progress of their 2 nm-class N2 chip development during their Open Innovation Platform (OIP) forum. The N2 chip will introduce various innovations, including nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM) capacitor. To take full advantage of these innovations, chip designers will need to use new electronic design automation (EDA) tools, simulation and verification tools, and IP.

TSMC ecosys

TSMC has worked closely with EDA partners, IP partners, and other stakeholders to ensure that the necessary tools and IP are available in advance. Major EDA tools from Cadence, Synopsys, Ansys, and Siemens EDA have already been certified by TSMC for N2 chip design. EDA software programs from Cadence and Synopsys are also ready for analog design migration. Additionally, Cadence's EDA tools already support N2P's backside power delivery network.

While progress has been made in terms of EDA tools and IP, some areas, such as non-volatile memory, interface IP, and chiplet IP, are still in active development or planned for development by companies like Alphawave, Cadence, Credo, eMemory, GUC, and Synopsys. TSMC's foundation libraries and IP, including standard cells, GPIO/ESD, PLL, SRAM, and ROM, are ready for mobile and high-performance computing applications.

Preparations for N2 chip production began long ago, with TSMC's Open Innovation Platform (OIP) supporting their partners in starting their work on products well in advance. Although significant progress has been made, there is still work to be done before the full ecosystem of tools and libraries for designing 2 nm chips is complete.

TSMC forecasts mass production for N2 in the second half of 2025, however delays may occur. At the same time, major players like Apple, Intel, NVIDIA, AMD, Qualcomm, and others are already working on their 2 nm chips and may be ready with their products by the time mass production starts. Smaller companies may also be able to begin their designs soon as preparations for N2 chips are well underway at TSMC and its partners.