AMD has introduced its latest chiplet-based System-on-Chip (SoC), the Versal VP9102, which is specifically designed to address the increasing complexity of chip designs in today's technology landscape. With fields like artificial intelligence, machine learning, and-performance computing pushing the industry forward, chip design, especially the testing and verification phase, has become more challenging than ever before.
To tackle these challenges, the Versal VP9102 SoC from AMD offers a promising solution. It consists of four individual dies, known as super logic regions (SLRs), making it a chiplet-based SoC that can alleviate the difficulties of chip testing and verification. Rob Bauer, senior product line manager for Versal at AMD, shared insights about the new SoC, emphasizing its significance in handling the complexity of modern chip designs.
The need for emulation SoCs is crucial in chip development. Since advanced chips are expensive to physically manufacture, designers need a way to verify the functionality of their designs before committing to production. That where emulation platforms, like FPGA-based SoCs, come into play. However, as chip complexity increases, the demands on these emulation platforms also rise. Bauer explains that cost estimates for advanced chip designs predict a staggering $700 million per design, with a significant portion allocated to verification and software development alone.
There are two key trends the need for enhanced emulation platforms. Firstly, the increasing gate count to keep up with compute-intensive applications like machine learning. Secondly, the rise of chiplets, where multiple dies are interconnected through advanced packaging technology. As chip designs become more intricate, emulation platforms play a critical role in ensuring their functionality. Bauer predicts that semiconductor devices five years from now will be significantly more complex, making emulation platforms even more vital.
The AMD Versal VP9102 SoC is an emulation class adaptive SoC designed to streamline and future-proof the emulation and prototyping phase of advanced chips. It offers a significant gate size, providing a total of 18.5 million logic cells, twice the capacity of the previous generation VU19P. Capacity is a crucial aspect of emulation and prototyping to keep up with technology's pace.
Supporting this substantial logic capacity is AMD's "quadrant-based architecture." The SoC comprises four individual dies or SLRs, interconnected using a network-on-chip (NoC). Each SLR incorporates programmable logic, a dual-core Arm A72 processing subsystem, a memory controller, SerDes blocks for high-speed connectivity, and a parallel digital communication interface (XPIO) for communication with other VP1902s.
The VP9102 SoC offers impressive performance specifications, surpassing its predecessor in terms of capacity and speed. Unlike traditional emulation platforms that run designs at lower rates, the VP9102's improved I/O bandwidth and capacity allow for higher clock rates closer to the eventual silicon speed.
As chip design becomes increasingly complex, it is essential to have improved technology for prototyping and emulation. AMD aims to provide a future-proof solution with the VP9102, offering increased capacity and faster speeds. The goal is to make advanced chip design more affordable and accessible.
AMD plans to start sampling the Versal Premium VP9102 adaptive SoC in Q3 to early access customers, with production projected for the first half of 2024.
