The steady shrinking of transistors within microchips is reaching the atomic level, with today's microchips containing over 100 million transistors in a space the size of a pinhead. However, the burgeoning number of these microelectronic devices is expected to consume a significant and rapidly increasing amount of energy. Projections suggest that by 2030, microelectronics could consume up to 20% of the world's energy.

To address this issue, the U.S. Department of Energy (DOE) has allocated $4 million to fund research at the DOE’s Argonne National Laboratory. This research aims to leverage atomic layer deposition (ALD) to develop new materials and devices for microchips, potentially reducing their energy consumption by up to 50 times. The project, set to commence in early 2024 and last for two and a half years, is part of the DOE’s Energy Efficient Scaling for Two Decades (EES2) program. Argonne will collaborate with Stanford University, Northwestern University, and Boise State University on this endeavor, led by Argonne Distinguished Fellow Jeffrey Elam.

The use of atomic layer deposition (ALD) in microelectronics is particularly promising, as it allows for the creation of ultra-low-power electronics with great precision. The technique, known for producing extremely thin layers, will be used to redesign microchips, aiming to eliminate the need for data shuffling and reduce energy consumption. Furthermore, the project will focus on developing an alternative 2D semiconducting material, molybdenum disulfide (MoS2), to replace silicon in memory chips and microprocessors. The goal is to reduce energy usage by effectively stacking memory and logic, potentially achieving a 90% energy reduction.

In conjunction with developing 2D-FETs and memtransistors using ALD MoS2, the research team will work on demonstrating the commercial viability of this technology by depositing MoS2 on large wafers at low temperatures. Collaborating scientists at partner institutions will specialize in different aspects of the project, and computational modeling will assess the energy efficiency and performance of these new devices.

This project represents a significant effort to address the growing energy consumption of microelectronics through the development of energy-efficient, low-power transistors and microchips, and the integration of advanced materials and manufacturing processes.