Rohm Semiconductor recently released its fourth generation of silicon carbide (SiC) MOSFETs. But do these components keep what the manufacturer promises? PGC Consultancy and TechInsights took a closer look.

By Prof. Peter Gammon (PGC Consultancy), Dr. Stephen Russell (Tech Insights)

When Rohm announced their fourth generation of silicon carbide (SiC) MOSFETs in June 2020, the press release stated , "The area-specific on-resistance is 40 percent lower compared to conventional products without sacrificing the short-circuit rating by using the original double-trench structure has been further improved«. It also said: "In addition, by significantly reducing parasitic capacitance, it is possible to reduce switching losses by 50 percent compared to our previous generation of SiC MOSFETs."

When the first products were available this year, TechInsights was able to procure a few copies and already presented the first sectional images in July 2022 [2] . Since then, PGC Consultancy has been working to provide electrical data on these devices which, combined with these cross-sectional views, should help evaluate Rohm's advancements in trench technology. The following are some insightful initial evaluations to examine the above claims made by the company and to understand the improvement actions taken.

Fundamentals of Trench MOSFETs
In conventional planar MOSFETs, the gate and channel regions are on top of the semiconductor. This type of building block is easy to craft and quite robust. However, in order to shrink the chip and thereby increase the number of chips per wafer (yield), the lateral topology limits the possibilities for how far the chips can ultimately be scaled down.

A trench MOSFET has its gate at the edge of a trench etched into the SiC surface. Such a trench gate reduces the on-resistance, more precisely the specific on-resistance (R on ·A). This allows the manufacturer to downsize the chip and make their product with less SiC material for a given R DS(on) , thereby increasing the number of chips per wafer.

For the lower R on·A of Trench MOSFETs are several reasons. First, at a gate fabricated on the sidewall of a SiC trench, electrons move faster in the channel, so they are less impeded than in a planar device. This reduces the channel resistance. Second, trench MOSFETs can potentially eliminate the resistance in the JFET region of a planar MOSFET. This is the area where the current of two channels is strongly crowded between the p-type contacts. However, as we shall see, a pragmatic design can lead to the reintroduction of a JFET-like region. Third, it should be possible to place more gates in vertical trenches than planar gates, reducing cell-to-cell spacing and increasing current density.

However, trench MOSFETs are difficult to optimize for reliability and robustness. This is because the high electric field in silicon carbide, which is nine times higher than in silicon, at the top of the device must be maximized while at the same time protecting the sensitive gate oxide, which is also located at the top of the device, from this field.

In order to master this balancing act, a sophisticated but complicated component layout is required. Otherwise, the drift area must be greatly oversized (derating), which negates the advantages of the trench architecture. A disadvantage of trench MOSFETs is therefore their more complicated design, which usually requires more manufacturing steps, some of which can introduce additional complications: deep implants created with high energy (in the case of Infineon) or deep trench etches (in the case of Infineon). Rohm's new Gen4).

Trench designs by Rohm and Infineon

Rohm and Infineon were the first to move to trench MOSFETs, using very different designs. Figure 1 provides a schematic comparison of various SiC MOSFET designs, including Rohm's Gen 3 and Gen 4. Figure 2 shows a section through the building blocks of Rohm's Gen 3. The company has gone for a more traditional design with channels on each side of the gate trench and uses source and blind trenches on each side with deep P implants protecting the gate trench.

Figure 1: Internal structure of various SiC MOSFET cells

Infineon, on the other hand, makes every trench work more intensively. Each trench has only one channel on one side, while the other side is surrounded by a deep P+ implant to keep the high electric field away from the gate oxide ( Figure 1 ). This arrangement allows the channel side of the trench to be perfectly aligned with the SiC crystal, which is offset by 4° – a clever trick to lower the electrical resistance of the crystal.

Figure 2 shows the two inactive source trenches between each active gate trench and the wide body contacts, making the cell spacing very large for a trench device. However, when looking at this device from above, this seemingly wasteful layout makes sense. Instead of the traditional striped gates that only span one dimension across the device, Rohm Gen 3 devices have gates that run both top-to-bottom and left-to-right. This creates a clever two-dimensional lattice of gates that nearly doubles the gate density per unit area. This concept is similar to Wolfspeed's hexagonal layout, which increases the gate density by a factor of 1.3.

Figure 2: Image of the previous Gen 3 of Rohm's SiC MOSFETs under the scanning electron microscope

However, none of the trench designs could boast a Ron·A lower than the market-leading planar MOSFETs until Rohm introduced the Gen 4. Another important question was how well the source trenches can protect the gate from the very high field strengths.

Gen 4 overview

Figure 3 shows a high-resolution scanning electron microscope image of a Gen 4 component. Compared to its predecessor ( Figure 2 ), this generation has some similarities and some noticeable differences. Similarly, the approach taken by Rohm remains to use a traditional trench design with channels on both sidewalls of the gate trench. However, each gate trench is now flanked on either side by a single grounded source trench that extends twice as deep into the drift region. The company cleverly uses this important design element to better protect the gate oxide and lower the on-resistance. More on that in a moment.

Figure 3: Scanning electron micrograph of Rohm's new Gen 4 SiC MOSFETs

Each individual dummy/source trench per gate trench reduces cell spacing by a factor of 3. However, this means the cell layout Rohm used in Gen 3, which nearly doubled gate density, was abandoned in favor of a traditional one-dimensional stripe layout Has. In total, the density of gate trenches per unit area increases by at least 50 percent. This further reduces the resistance in the channel region that other SiC devices struggle with. This can be as much as 30 percent of the on-resistance of a 650V planar MOSFET.

Another important factor influencing resistance, the substrate, has been thinned for the first time, significantly reducing its proportion.

Silicon Carbide, Peter Gammon, PGC Consultancy, Rohm
Figure 4: Rohm's Gen 4 MOSFETs have lower Ron·A and lower Coss and Crss values
© Rohm
Rohm's first claim was that conduction losses dropped by 40 percent, allowing the size of the chip to be reduced [4] . In fact, the TechInsights cross-sections confirm that the on-resistance R on A of the chip's active area is almost exactly 40 percent lower than the previous generation, although the necessary non-active areas of the device only marginally reduce this benefit ( Fig 4 ). In addition, the R is on·A 20 percent lower than the leading planar device characterized by PGC. This development is critical because it allows the chip to be shrunk, which in turn increases the number of chips per wafer and reduces costs [5] .

The second statement in Figure 4 states that the switching losses are reduced due to the lower Miller capacitance. While the compared chips were not a perfect match, it was confirmed that C rss (at nominal voltage) was reduced by about 90 percent and C oss (depending on voltage) by a fraction. Benchmarking tests on the switching behavior are currently still running at PGC Consultancy.

Rohm claims under scrutiny
To verify Rohm's initial claims regarding these devices, a 750V-rated Gen 4 MOSFET was compared to a 3rd generation 650V MOSFET and a market-leading 650V planar MOSFET. All specimens had similar on-resistance ratings.

Figure 4: Rohm's Gen 4 MOSFETs have lower Ron·A and lower Coss and Crss values

A statement from Rohm refers to the fact that the voltage rating of the product line has been increased from 650 to 750V. The company explained: "The breakdown voltage of 750 V ensures design flexibility against voltage spikes at U DS". This could be an interesting development to see across the industry.

Figure 5: Despite a higher nominal voltage, the measured breakdown voltage drops from Gen 3 to Gen 4. This significantly reduces derating in the drift range.

In fact, the breakdown voltage of the new Gen 4 device is around 1000V under static test conditions, lower than that of the Gen 3 device which is over 1200V ( Figure 5 ). This puts the Gen 4 device on par with the leading planar MOSFETs. Given the available data, this smaller margin of safety is quite astounding. According to Rohm, these devices should be able to operate at 75 percent of their actual breakdown voltage, compared to just over 50 percent for the Gen 3 - a sign that they are much more reliable. This lower derating is a major improvement that, among other things, helps reduce on-resistance, as discussed below.

Figure 6: The short-circuit strength of the Gen 4 MOSFETs should be higher and the Ron A lower at the same time.

A short-circuit test of the Gen 4 at PGC will follow shortly, because a third interesting statement from Rohm is that despite smaller chips and higher current density, the short-circuit resistance has increased contrary to expectations ( Figure 6 ). Along with the lower derating, this is further proof that the company has taken a big step forward in the reliability and robustness of its components.

All in all, Rohm has delivered a remarkable achievement that refutes many criticisms of early SiC trench components. But how was this possible?

The first commandment: protect the gate oxide!

Figure 7: Not to scale representation of Gen 4 vs. Gen 3 SiC MOSFETs. The electric field lines show how the gate oxide is protected.

Picture 7 schematically compares the cell structures of gen 3 and gen 4. The figure is not to scale but highlights the changes around the gate. When designing MOSFETs, especially SiC Trench MOSFETs, the main concern is to protect the gate oxide in the off-state when a high voltage is present between the drain and source. At this point, there are high electric fields at the surface of the device, which can lead to problems related to gate oxide leakage and reliability. In the Gen 3 device, the source trenches are only as deep as the gate trench, so the underlying P+ implants were only slightly deeper than the gate trench itself.

In contrast, the source trenches of the new Gen 4 are much deeper with their P+ regions. As a result, the pn junction that protects the gate is further down in the drift region and thus further away from the gate oxide. This keeps the maximum field strength further away from the gate oxide than with Gen 3.

The benefit of gate protection
When the gate is less well protected, as in the Gen 3 device, it is important to ensure that the electric field never becomes strong enough to damage the gate oxide. Therefore, the drift range, which has to absorb the blocking voltage, is deliberately oversized (derating [3] ). It should be remembered that a 650V Gen 3 device, such as can be used in electric cars with 400V battery voltage, has a breakdown voltage of over 1200V. This ensures safe, long-life operation, but the resistance of the drift region increases exponentially with the voltage it must carry (R dr ∝ U 2.28 ).

Since the gate is better protected in Gen 4 devices, their drift region does not need to be overdesigned as much. The measured breakdown voltage was 1000 V, a reduction of more than 20 percent compared to Gen 3. Thus, the resistance in the drift region could be reduced by more than 40 percent. This seems to be confirmed in the TechInsights cross-sections, as the drift region of the new device is similarly wide, although it is actually thinner due to the deep trenches (see Figure 7 ). It can also be assumed that the drift region is more highly doped on Gen 4, further lowering the resistance.

In addition, reliability also increases when the gate oxide is effectively protected. This also explains the longer lifetime of the gate oxide in the short circuit, which Rohm has increased from a minimum of 4.5 µs to 5.5 µs. In the event of a short circuit, the area of ​​the component that absorbs the highest field usually reaches the highest temperatures. The further away this point is from the gate, the longer it takes for its oxide to break through.

A step towards SiC superjunction?
Even though the new Gen 4 are not superjunction devices, since their p-type trenches are only a fraction of those we propose, it is reasonable to assume that the superjunction principle is at work in the region below the source trenches. Finally, a very narrow n-doped region sandwiched between two P-pillars could cause the JFET's resistance to increase significantly. However, the resistance in the n-doped region is likely to be higher than in the drift region, so that the principle of charge balancing in superjunction MOSFETs can be used to increase the doping without affecting the blocking capability.

Summary and conclusions
The Gen 4 design seems to be realizing its potential. From this it can be concluded that Rohm found a way to use their deep trench design to simultaneously:

  • reduce the cell pitch by a factor of three, which significantly reduces the channel resistance
  • protect the gate oxide, increasing its reliability and allowing for less derating of the drift region, decreasing its resistance
  • significantly reduce the substrate resistance and to introduce a JFET region, although this disadvantage can be reduced by the principles of charge balancing (superjunction).
    Now it remains to be seen to what extent EV manufacturers and Tier 1 companies will use this technology in their on-board chargers or possibly even in the traction converters. This is because planar SiC MOSFETs still dominate in this area.