Moore's Law, a principle governing the scaling of electronic devices, predicts that the number of transistors on a chip will double every two years, leading to increased computing power. However, the challenge of fitting more and more transistors into a confined space has become increasingly difficult as current technology advances. In a recent study published in the journal Nature, researchers from Penn State propose a solution: the seamless integration of 3D stacking with 2D materials in semiconductor technology. This approach not only allows for increased packing of silicon-based transistors onto a computer chip (referred to as "More Moore"), but also enables the use of transistors made from 2D materials to provide diverse functionalities within different layers of the stacked structure (referred to as "More than Moore").
The study demonstrates the feasibility of achieving both "More Moore" and "More than Moore" through monolithic 3D integration, which involves directly fabricating devices on top of each other. This approach offers the highest density of vertical connections and enables more space for making connections without relying on bonding pre-patterned chips.
One significant challenge faced in monolithic 3D integration with conventional silicon chips is the process temperature ceiling of 450 degrees Celsius. However, the use of 2D materials, such as transition metal dichalcogenides, allows for lower process temperatures, addressing this challenge and enabling successful monolithic 3D integration.
The researchers achieved monolithic 3D integration at scale using 2D transistors made with transition metal dichalcogenides, thus adding new and useful features to electronic devices and making gadgets smarter and more versatile. Additionally, the vertical stacking of devices in 3D integration contributes to more energy-efficient computing by reducing distance, lag, and power consumption.
The researchers used existing techniques to achieve this, but they are the first to successfully implement monolithic 3D integration at this scale using 2D transistors. This achievement was made possible by the availability of high-quality, wafer-scale transition metal dichalcogenides developed by the Two-Dimensional Crystal Consortium (2DCC-MIP) at Penn State, which is a U.S. National Science Foundation (NSF) Materials Innovation Platform and national user facility.
The study's implications include potential future partnerships between academia and industry, with industry leveraging Penn State's 2D materials expertise and facilities. The breakthrough in scaling could lead to advancements in the semiconductor industry and U.S. competitiveness.
The technological advancement demonstrated in this study is considered a significant first step, demonstrating the translation of research to a scale appreciated by the semiconductor industry. The successful integration of a large number of devices at wafer scale positions Penn State uniquely to lead in partnering with the U.S. semiconductor industry for further advancements in this research.
Furthermore, the study characterized tens of thousands of devices, bridging the gap between academia and industry and demonstrating the potential for future collaborations and technological advancements in the semiconductor industry.
The research was supported by the NSF and Army Research Office.
