Business Unit - Semiconductors
Using 3D integration of components, complex, heterogeneous system-in-packages (SiP solutions) can be developed.
The major advantages of 3D system architecture include:
High miniaturization and improved form factor
Improved performance and power efficiency thanks to the faster signal speeds and higher bandwidth via shorter and narrower signal paths
Increased functionality due to heterogeneous integration of components, which are fabricated using various techno logies (sensor, memory, ASIC and transceiver)
Faster product implementation (also known as ‘time to market’)
Fewer costs due parallelization of assembly processes
Fraunhofer IZM’s services include a closed process chain – concept and process development, characterization, as well as reliability assessment and prototyping of 3D systems. All processes required throughout the chain for the realization of wafer-level packages, including through silicon via (TSV) formation, are available in our labs. 3D systems that meet the disparate target profiles demanded by various application scenarios, such as image sensors, sensor nodes, eGrains, can be realized and characterized. We work in close cooperation with tool and material suppliers to continuously improve applied technologies.
Hermetic sealing of MEMS components on wafer-level
Through silicon-via technologies offer many advantages in the integration of various components, including sensors, ASICs,memories, transceivers, into a stacked architecture that features excellent performance and small form factor. Together with industrial and academic partners, Fraunhofer IZM develops base technologies for the wafer level fabrication of low-cost, miniature, chip-scale packaged (SCP) hybrid microsystems. For this purpose, standard technologies like redistribution, TSV formation and wafer-to-wafer bonding are combined to produce versatile approaches for hermetic wafer-level packaging of MEMS components.
Some of these new developments were funded by a collaborative project Go4Time, which was part of the EU’s 7th FRP. The overall goal of the project was the development of manufacturing concepts for highly stable, generic, low-cost timing devices suitable for power aware, long autonomy and portable telecommunication systems such as mobile phones. One milestone in this project was the wafer-level fabrication of a MEMS package consisting of an active CMOS wafer with vertical copper-filled TSVs and bonded cap wafers for hermetic sealing of resonator components.
Services relating to 3D-Integration
Temporary wafer bonding for handling and processing of thin wafers
Permanent wafer to wafer bonding
Integration of passive components into thin film multi-layer wiring systems