ChipMOS TECHNOLOGIES INC. ("ChipMOS"), listed on the Taiwan Stock Exchange Market in April, 2014 (TWSE: 8150), is a leading independent provider of total semiconductor testing and packaging solutions to fabless companies, integrated device manufacturers (IDM) and foundries. ChipMOS merged with its parent company, ChipMOS TECHNOLOGIES (Bermuda) Limited in October, 2016. Consideration of the merger was the combination of cash and newly-issued American Depository Shares (ADS) trading on the NASDAQ Stock Market with ticker of “IMOS”.
We provide a full range of back-end testing services for high density memory, mixed-signal and display driver semiconductors. In addition, we offer a comprehensive selection of leadframe-based and organic substrate-based package assembly services for memory, mixed-signal, and display driver semiconductors which are used in diverse end-use markets, including personal computers, communications equipment, office automation and consumer electronics. Our testing and packaging services are provided, pursuant to customer’s request, on an independent or a turnkey basis.
With operations headquartered in Taiwan, the heart of the world’s technology value chain, most testing is currently conducted at our facility in the Hsinchu Science Park, while semiconductor packaging services are primarily conducted at our Southern Taiwan Science Park facility. We also provide gold bumping services at Chupei, Hsinchu. All of our facilities are state-of-the-art and reflect our long-standing commitment to our customers with the best technology and support services leading, innovative customers deserve.
In addition to our unique back-end solutions, we work in collaboration with our global client base to provide a complete range of vertically integrated solutions from package design through drop-shipment. This total solution capability is critical given compressed product lifecycles and the need for streamlined, efficient supply chain partners.
Close collaboration between our R&D teams and customers ensures technology roadmaps synchronized with production readiness of new test and package solutions for increasingly sophisticated semiconductor products. Growing with our customers leverages and expands our deployment of advanced engineering skills and capabilities for ongoing cost reductions, such as software conversion programs and parallel testing for client testing operations.
ChipMOS provides full turnkey services to LCDD drivers, memory and logic mixed-signal products. Our turnkey solution includes services from wafer bumping/RDL, wafer sort, assembly, final test, and drop shipment. We are aiming to create a one-stop shopping type of semiconductor backend services to our customers for the considerations of time to market and cost of ownership.
WLCSP Technology
Wafer-level Chip Scale Package (WLCSP) is the packaging technology for IC chips still in the form of wafer, compare to the conventional method of dicing the wafer into individual chip and then packaging them. WLCSP is essentially a true chip scale package (CSP) technology, since package is the same size as the silicon chip. Wafer-level packaging allows the integration of wafer sort, packaging, final test, and burn-in test at wafer level in order to streamline the manufacturing process. WLCSP is a process designed to complete packaging and testing operations of semiconductor devices before wafer dicing. Normally, semiconductor devices will be placed in the carrier tape after dicing and sealed with the cover tape in order to protect the IC for subsequent processing. WLCSP provides the best solution to meet the requirements of small foot print, light weight, and miniaturization for the devices to be used in communication products like cellular phones, TWS and other portable electronics. WLCSP generally employ lead free solder balls to form joints with substrate in order to provide electric connections. The solder joints serve the purpose to reduce the stresses resulting from the thermal mismatch between substrate and device as well in order to enhance the service reliability.
ChipMOS provides the BOP (Ball on Pad, 4 masks) and BOT (Ball on Trace, 3 masks) solutions to customers.
To provide customers with complete services, ChipMOS acquired Advanced Micro Chip Technology (AMCT) in April 2004 and since then ChipMOS has success fully extended its services for LCD driver from packaging and testing up stream to wafer bumping. In terms of market share, ChipMOS currently delivers more than 40% of the LCD drivers packaged in Taiwan with gold bumping technology.
Not only gold bumping technology, ChipMOS also successfully develop and reach mass production for widely bumping services such as MCB, RDL, Copper pillar bump and Ball drop applications.
ChipMOS offers a broad range of package families designed to provide our customers with an array of packaging solutions. The packages available include leadframe-based packages, such as the small outline package (SOP), thin small outline package (TSOP) and quad flat package (LQFP/TQFP); and the substrate-based packages, such as FBGA, VFBGA, stacked CSP, TFBGA, LGA, TCP, COG and COF. Aimed for optimum device performance, ChipMOS employs state-of-the-art Computer Aided Engineering (CAE) simulation techniques, for both electrical and thermal analyses, to facilitate package design and manufacturing parameter optimization. Customers are able to make good use of ChipMOS' technical capability by inputting their information on the "Design Center" or "Package Characterization" pages of our website.
To be competitive and provide a leading edge advantage to our clients, ChipMOS, working jointly with our material and equipment vendors and customers, has focused significant resources on the development of advanced packaging technologies, including: Wafer Level CSP, 3D technology, Flip Chip CSP, environmentally friendly green package, System-in-Package technology, Known Good Die technology, MEMS and display driver IC(DDI) packages such as chip on film (COF) and chip on glass (COG).
