SUMCO provides high-quality silicon wafers supporting the semiconductor industry at the leading edge. Raw materials with the highest level of quality are used as the silicon wafer material. The wafers are produced under the strictest quality control to create products meeting customer needs in all kinds of ways.
Made from the finest raw materials, for quality that can be counted on
The silicon wafers provided by SUMCO are made from high-purity monocrystalline silicon ingots, manufactured by the CZ (Czochralski) crystal growth process. Ingots up to 300mm in diameter are manufactured under the highest level of quality control.
If required by customers, we also make use of the MCZ (Magnetic Czochralski) technique, applying a strong magnetic field to the molten silicon, or the FZ (Float-Zone) technique whereby monocrystalline ingots are grown at low oxygen levels without using a quartz crucible.
Ultra-flat, ultra-clean wafers produced under strict quality control
Polished Wafer (PW)
A monocrystalline ingot is sliced to thicknesses of around 1mm and the surfaces are polished to a mirror finish. As a result, the wafers are exceptionally flat and clean. SUMCO can also add gettering capability to the wafer, by which heavy metal impurities that can degrade electrical properties are captured.
Wafers with improved surface crystal perfection thanks to high-temperature annealing
Annealed Wafer (AW)
A polished wafer undergoes high-temperature annealing in an atmosphere of hydrogen or argon, removing oxygen near the wafer surface. The resulting wafer has improved crystal perfection.
Wafers with a vapor phase growth layer of monocrystalline silicon
Epitaxial Wafer (EW)
For superior quality, the surface layer of the polished wafer is formed from monocrystalline silicon using vapor phase growth, or epitaxy.
Wafers with a layer for embedding integrated circuits
Junction Isolated Wafer (JIW)
First the customer’s design is followed to form an embedding layer for integrated circuits on the surface of the wafer employing photolithography, ion implantation, and thermal diffusion techniques. An epitaxial layer is then formed on top of this layer.
Wafers with an oxide layer under the active layer for higher integration
Silicon-On-Insulator (SOI) Wafer
An oxide layer with high electric insulation is sandwiched between two polished wafers, which are then bonded together. This enables devices with high integration, low power consumption, high speed, and high reliability. A diffusion layer of arsenic (As) or antimony (Sb) can also be formed in the active layer at the wafer surface.
Wafers can be recycled on request
Reclaimed Polished Wafer (RPW)
On customer request, used wafers can be taken back and recycled for reuse.
Dopants for adjusting conductivity B (boron), P (phosphorous), Sb (antimony), As (arsenic)